AlixLabs, a Swedish semiconductor equipment developer, has begun a six-month evaluation of its Atomic Layer Etch Pitch Splitting (APS™) technology inside the NanoIC pilot line coordinated by imec in Leuven. The engagement gives the startup access to imec's lithography, process integration, and metrology capabilities — the three disciplines that decide whether a pitch-splitting scheme survives contact with a production-representative flow.

The timetable is concrete: six months from start to verdict. During that window, imec will exercise the APS process on its pilot line toolset and characterize the results with the same metrology used for advanced-node development lots. That matters for buyers of patterning equipment. A single-tool demo in an isolated chamber tells you almost nothing about overlay, CD uniformity, or defectivity at die level. A pilot-line evaluation, run against a reference flow, does.

What pitch splitting has to do

Pitch splitting exists because lithography cannot, economically, print the tightest pitches directly. Classical spacer-defined pitch splitting — the self-aligned double and quadruple patterning used since the 22/16 nm nodes — deposits a conformal film over a printed mandrel, etches it back, removes the mandrel, and uses the remaining spacers as a hard mask. Feature density doubles each cycle. The cost is process length: film deposition, multiple etch steps, and mandrel removal, each adding cycle time and defect opportunity.

AlixLabs proposes to collapse part of that staircase. Its APS approach applies atomic layer etching — a cyclic, self-limiting process in which each activation-and-removal cycle strips a controlled sub-nanometer dose of material — to divide a printed feature into two or more features directly. In principle, self-limiting ALE chemistry offers etch-depth control and selectivity that continuous plasma etching cannot, because the reaction stops when the activated surface is consumed rather than when a timer expires. Whether that precision transfers from single features to full fields, with the line-edge roughness and CD control that logic and memory customers specify, is exactly what a pilot line exists to measure.

Measured performance versus claims

At this stage, the announcement carries no CD uniformity numbers, no overlay deltas, no throughput figures, and no defectivity data. Those are the metrics an integration engineer will ask for first, and they will have to come out of the imec evaluation rather than the press release. The NanoIC pilot line provides the reference processes and metrology to generate them under conditions that resemble manufacturing rather than a laboratory bench — which is the point of running the evaluation there instead of at AlixLabs' own facility in Lund.

For process engineers, the items to watch over the next six months are the standard set: CD mean-to-target and uniformity across wafer and field, LER/LWR on the split features, etch selectivity to underlying films, and overlay of the split level to upstream and downstream layers. Any one of them can disqualify a pitch-splitting method regardless of how elegant the chemistry is.

The adoption question

The commercial stake is straightforward. If APS can deliver pitch halving with fewer deposition-and-etch cycles than spacer-based schemes, it shortens one of the longest and most expensive module sequences in advanced patterning — relevant both to leading-edge logic and to the dense array levels of 3D NAND and DRAM. If it cannot, the six months at imec will show where the physics breaks.

The question the evaluation raises for process owners: is there room, in a roadmap dominated by EUV single-exposure and self-aligned schemes, for an ALE-based pitch splitter that sidesteps part of the deposition stack? The imec results — published or not — will shape how seriously fab integration teams take the answer.