CPO Standard Sets Rack Rules; Wafer Supply Chain Sets the Limit

Nineteen companies, led by Lightmatter, published a white paper in August 2026 through the Open Compute Project (OCP) that specifies a standardized architecture for copackaged optics (CPO) in AI infrastructure. The Open Silicon Photonics for AI Systems initiative defines a common multivendor reference architecture intended to let AI clusters scale from 72 nodes to more than 1,024 nodes while staying interoperable across switch vendors, XPU generations, and SerDes speeds. René Jonker, chief product officer at Soitec and author of the analysis, argues the standard answers only half the question: whether the substrate supply chain beneath it can produce photonics-grade silicon-on-insulator wafers at the required volume, tolerance, and speed.

Why copper ran out of reach

The white paper lays out the physics driving the move to centralized CPO. As SerDes rates climb toward 448 Gbps per lane, copper's usable reach shrinks to tens of centimeters — well short of what a multi-rack scale-up domain requires. Earlier interconnect generations absorbed longer copper runs by trading signal margin. At 448G, the reach is simply not there, and the usual compensations make matters worse: retimers and redrivers buy distance by spending power and adding latency, the exact trade a scale-up fabric can least afford. Jonker notes that vendors building toward these speeds independently reach the same conclusion — optics must move inside the package — and that convergence is one reason a shared architecture is achievable now in a way it was not three years ago.

The past two years of CPO work, by contrast, produced point solutions. Each hyperscaler negotiated its own design, thermal budget, and optical I/O density with whichever vendor committed to a roadmap. Test infrastructure was rebuilt, connector tooling requalified, and thermal solutions redesigned around packages that differed mechanically but not architecturally. Little of that work carried from one deal to the next.

How tight are the wafer tolerances?

Photonics-SOI is the foundation for CPO, and its manufacturing tolerances are far tighter than those of the RF-SOI and partially depleted SOI (PD-SOI) substrates the industry has produced at scale for two decades. A Photonics-SOI wafer carries a top silicon device layer thinner than 220 nm on a buried oxide layer ranging from 50 nm to several microns. That top layer is the waveguide core, so its thickness is an optical parameter, not merely a mechanical one.

RF-SOI applications tolerate thickness variation across a wafer of a few nanometers without meaningful performance loss. Photonics-SOI cannot: the uniformity requirement is roughly an order of magnitude tighter, because small variations in silicon thickness change the waveguide's effective index and shift optical phase as light travels down it. Push the drift far enough and modulator extinction ratios degrade, ring resonators fall out of resonance, and the yield of an entire optical engine collapses. Resonant devices are least forgiving — a drifted ring can often be pulled back with a thermal tuner, but every milliwatt spent heating a ring subtracts from the power budget that justified copackaging. Most of these failures surface at optical test, after the wafer has accumulated its full packaging and assembly value.

A module hardware system (MHS)-based CPO architecture can specify optical I/O density, connector pitch, and power envelopes precisely. It has no mechanism to specify how a wafer supplier maintains buried-oxide and top-silicon uniformity across a 300-mm substrate at hyperscaler volumes. Layer transfer, Jonker writes, is a process where learning is empirical and cumulative.

Does CPO multiply photonic silicon demand?

Not in the way a loose version of the argument holds. Moving an optical engine from a faceplate module into the package does not change how much photonic die area a given bandwidth requires — a 51.2T switch needs 51.2T of electro-optic conversion whether it happens in 64 pluggables or eight copackaged engines. But three real mechanisms do change the wafer math:

• Material substitution. A large share of today's high-speed pluggables use indium phosphide (InP) with electro-absorption modulated lasers (EMLs), volume that never touches a Photonics-SOI wafer. CPO designs are effectively all silicon photonics, converting a substantial block of transceiver demand from III-V substrates to photonics-grade SOI — structural rather than opportunistic, and already underway under well-documented InP and EML capacity constraints.
• Optics intensity. The number of optical lanes surrounding each accelerator rises faster than compute die area; each new platform packs more optics around roughly the same silicon.
• Scope. Scale-up domains that were copper become optical — photonic content that did not previously exist and scales with the size of the coherence domain, not the number of racks.

If directionally right, Jonker writes, OCP's success depends on the photonics-grade substrate supply chain scaling several times faster than the pluggable-optics supply chain it displaces — at a moment when the number of qualified suppliers of 300-mm photonics-grade SOI remains small. Foundries have built capable platforms, such as GlobalFoundries' Fotonix and Tower's PH18, and each depends on photonics-grade SOI as starting material. Standardizing the rack architecture adds no capacity at this layer; it makes demand more predictable and likely larger.

What should standardization mean for substrate suppliers?

When hyperscalers request different package sizes or power budgets, substrate suppliers certify a dozen near-identical wafer versions, each with its own lot history, reliability data, and yield learning. Volume fragments across SKUs that never reach efficient scale. A shared reference architecture consolidates roadmaps around fewer specifications and shortens lead time to add capacity, because equipment can be committed against a spec that will still exist three years later.

Interoperability also needs a definition at the material level. The white paper's technology-neutral stance on silicon photonics, VCSELs, and micro-LEDs is reasonable architectural policy, but each approach demands different wafers even when it ends at the same connector. Jonker calls for agreed metrics and measurement methods for thickness uniformity, defectivity, and surface roughness, so a foundry can state a requirement once instead of negotiating it bilaterally with every supplier.

Why energy efficiency traces back to the wafer

Waveguide insertion loss depends on sidewall roughness and thickness uniformity of the top silicon layer. Excellent uniformity lets designers run optical links at lower laser power for the same bit-error-rate target; marginal uniformity forces higher laser drive current, more aggressive forward error correction, more conservative link margins, and more thermal tuning — each negating the power savings that justified CPO. No amount of switch or package engineering recovers optical performance lost to a non-uniform substrate.

The initiative's breadth — spanning system integrators, ODMs, test equipment makers, and chip designers — shows the industry understands no single company's roadmap solves CPO. Architecture standardization is a coordination challenge, tractable as the 19-company white paper demonstrates. Materials readiness is a manufacturing physics challenge that coordination alone cannot solve. The next phase, Jonker writes, must treat substrate qualification and supply capacity as a first-class element of the standard: published substrate requirements alongside the rack spec, agreed measurement methods, and enough demand visibility for suppliers to commit capital.