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TI's 3-GSPS ADC Catches Nanosecond Power Glitches on AI Rails

TI's ADC34DSO75 samples at 3 GSPS with 3 GHz bandwidth to catch nanosecond voltage glitches on AI processor rails, using event-based telemetry to replace FPGA-based monitoring.

By Olivia Hart4 min read801 words

Features

  • The ADC34DSO75 samples at up to 3 GSPS with 3 GHz full-power input bandwidth and 68-dB SNR.
  • AI processors can produce load transients exceeding 2000 A/µs, with peak power 50–60% above rated TDP.
  • Power consumption is 1.6 W per channel at full sampling speed, with 256 kB of on-chip memory across four channels.
  • A companion SOM pairs two ADCs to monitor up to eight voltage rails with nanosecond resolution.
  • Blackwell-based racks reach 120 kW, with next-generation Rubin racks specified at 600 kW.
High-Speed ADC Tracks Power Ups and Downs of AI
Device photoHigh-Speed ADC Tracks Power Ups and Downs of AI — AI-generated

Texas Instruments' new ADC34DSO75 samples at up to 3 gigasamples per second (GSPS) with a full-power input bandwidth of 3 GHz — fast enough, the company says, to capture nanosecond-scale voltage glitches on the power rails of AI processors. Introduced at the Open Compute Project's annual conference, the four-channel, 14-bit converter targets a problem that millisecond-rate server telemetry cannot see: load transients on NVIDIA Blackwell and AMD Instinct GPUs that swing from near-idle to full power almost instantly, with peaks reaching 50% to 60% above rated thermal design power (TDP).

Karthik Vasanth, VP and GM of data converters at TI, frames the stakes: "When there's a blackout, that's a very dramatic event that can bring the entire AI data center down. But there is a more subtle problem, which is a brownout, where you have a small voltage glitch on one of these racks, and that puts the model or a portion of the model out of commission." He added that because AI models span an entire data center, even brief outages are no longer acceptable.

What outpaces today's telemetry?

The physics is straightforward. AI workloads draw power in short, sudden bursts during computationally intense phases of training or inference. As processors shift from idle to full load, they generate di/dt slew rates above 2000 A/µs at the processor and more than 2.5 A/µs at the power supply unit (PSU), outpacing rack-level supplies and board-level voltage regulators. The result is undershoot, overshoot, and rail glitching within nanoseconds — even with dense decoupling capacitors near the die. In a single millisecond, a server can experience several nanosecond-scale events.

Blackwell GPUs already burn more than 1 kW each, with TDP ratings up to 1,400 W, and Blackwell-based racks reach 120 kW, with next-generation Rubin racks specified for 600 kW. Most existing telemetry samples at millisecond intervals, catching server-level droop but missing rail-level transients entirely — a blind spot where power, thermal, and utilization all look normal while intermittent faults persist.

How does the ADC resolve millivolt swings?

The converter combines its 3-GSPS sampling with on-chip digital signal processing. Modern AI cores run at 0.8 V to 1.2 V (VCORE), where tens of millivolts of fluctuation can destabilize a processor, so noise floor matters as much as speed. TI specifies a 68-dB signal-to-noise ratio (SNR) with low phase and amplitude noise for that reason. Power draw is 1.6 W per channel at full sampling speed, low enough for continuous in-server monitoring.

To avoid flooding the system with data, the ADC uses event-based telemetry rather than continuous logging. Each channel carries an independent event-detection engine that triggers capture only on programmed conditions:

  • Voltage above or below specified limits
  • Rate of change within a defined time window
  • Pre-trigger and post-trigger samples stored in 256 kB of on-chip memory, divided among the four channels

Because only events are captured, a small MCU can offload the data, eliminating the costly, power-hungry FPGA that nanosecond-scale monitoring usually requires. "You can program what you're looking for, and when that event actually happens, you store the information in memory," said Matthew Hann, product line manager for high-speed data converters at TI. "It's like having an oscilloscope for each node without the bulkiness of an oscilloscope."

How does it scale across a data center?

Multiple ADCs daisy-chain through a single octal SPI interface to the MCU, letting hyperscalers add channels to whatever rails they consider contentious. TI also introduced a system-on-module (SOM) pairing two ADCs to monitor up to eight rails, with external flash memory that preserves captured data through a blackout. "Think of this as a black-box recorder," Vasanth said.

Hann positions the device as location-agnostic: PSU monitoring still focuses on millisecond events, while tightly regulated PCB rails need nanosecond visibility, and the ADC34DSO75 handles both. "What we've designed is a high-speed, fully remote, and highly efficient watchdog for the most critical power infrastructure," he said. He also claims it is thousands of times faster than current solutions — a vendor figure; independent test data is not yet published.

TI argues that accumulated transient records open a path to predictive fault detection: by analyzing events over time, engineers can spot patterns that precede brownouts and degradation, building models that flag failures before they occur. That matters commercially, since a single outage can cost hundreds of thousands of dollars per hour, and hyperscalers now target automotive-grade reliability or better. The open question is whether event-based capture at the rail, rather than full-waveform recording, gives operators enough evidence to meet those reliability targets in audited deployments.

via edge.prnewswire.com (Original)

Filed under

  • texas-instruments
  • adc
  • power-monitoring
  • ai-infrastructure
  • data-converters
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Market editor covering technology and product news in Instruments, test and measurement at Testbench Report.

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