Gate-All-Around and Chiplets Push Metrology to New Limits

Semiconductor metrology now faces a twofold demand: characterise three-dimensional structures such as gate-all-around transistors and stacked nanosheets, and do it reliably at production speeds. That's the core argument of a contributed analysis by Peter Lawson on metrology's expanding role in semiconductor manufacturing, and it lands at a moment when feature control and yield are inseparable.

The physics hasn't changed, but the geometry has. Gate-all-around devices surround the conducting channel with gate material to improve electrostatic control as dimensions shrink. Stacked nanosheets add more complexity, with performance depending on the dimensions, spacing and uniformity of multiple closely packed structures. Top-down imaging alone can no longer characterise sidewall profiles, buried interfaces and cross-sectional dimensions. The takeaway: measurement strategies have to combine high-resolution reference techniques with faster methods suited to routine production monitoring.

What still works — and where it strains

Critical dimension (CD) metrology remains fundamental to process control, because widths, heights, profiles and uniformity of patterned features directly influence transistor performance and yield. Even small variations matter when repeated across billions of structures on a single chip.

CD-SEM (critical dimension scanning electron microscopy) measures line widths, contact hole diameters and pattern profiles where optical techniques lack spatial resolution. But a reliable measurement isn't simply about resolving a smaller feature. Image contrast, material composition, electron-sample interaction and boundary-finding algorithms all shape the reported result — at nanometre scales, defining where a feature begins and ends is a measurement science problem in its own right.

Optical methods complement it. Scatterometry and spectroscopic ellipsometry infer dimensional and material properties from how light interacts with patterned structures and thin films. They're fast and useful for across-wafer monitoring, but they interpret signals through mathematical models, so their accuracy depends on model quality, structural assumptions and reference measurements. AFM (atomic force microscopy) adds surface topography data, though speed, geometry access and probe effects limit high-volume use. These techniques are complementary, not interchangeable — selection depends on the feature, the required uncertainty, the process stage and the time available.

Why overlay is no longer just about targets

Devices are built through repeated lithography, deposition and etch cycles, so the relative positioning of successive patterned layers — overlay — is critical. Misalignment affects electrical connectivity and ultimately the proportion of functional chips per wafer.

Optical overlay systems measure dedicated targets rapidly and feed corrections to lithography equipment, compensating for wafer distortion, stage positioning and process-induced changes. The catch: with complex 3D geometries, an accessible target doesn't necessarily reveal every alignment issue inside a device, particularly buried features. That pushes fabs toward combining metrology sources and understanding each one's limitations before acting on the data.

Cross-sectional transmission electron microscopy can resolve extremely small structures and interfaces, but sample prep is destructive and the examined area is limited. Different techniques measuring the same feature can legitimately disagree — differences in physical principle and boundary definitions must be understood, not treated as one instrument being wrong. In plain terms: comparability between methods is now an engineering deliverable in its own right.

What does advanced packaging change?

Advanced packaging — combining multiple dies or chiplets into integrated systems — extends metrology beyond transistor fabrication. Hybrid bonding, which forms electrical and mechanical connections between closely aligned surfaces, depends on surface topography, cleanliness, alignment accuracy and interface condition. Small variations in flatness, local defects or relative positioning degrade bonding quality and connectivity.

The measurement task becomes multidimensional: surface topography, local height variation, wafer distortion, alignment and defects may all need evaluation within one production flow. This opens opportunities for optical surface measurement, interferometry, high-resolution imaging and automated inspection — and raises the value of integrating metrology at each production stage, so problems surface before expensive downstream assembly.

Can AI close the loop?

The commercial value of metrology lies in speed to decision, not just resolution. High-volume production generates large datasets across process steps, and statistical process control provides the established framework for monitoring variation. Automated data analysis increasingly identifies patterns, correlates measurements across stages and helps engineers trace defect causes.

AI may extend this through automated image analysis and anomaly detection, but Lawson is clear about the caveat: a system that consistently identifies a feature doesn't guarantee its reported dimension is accurate. AI-assisted metrology raises questions of model validation, repeatability and reliability under changing process conditions, and measurement systems must still be evaluated against suitable references with understood uncertainty.

Sampling compounds the problem. High-resolution measurements detail a few features, while production decisions need variation data across entire wafers and populations. Manufacturers must balance resolution, sampling strategy, throughput and cost — a highly detailed measurement is useless for control if it can't be taken often enough to catch process changes.

The open question for fabs and toolmakers alike: as architectures grow more demanding, will the combination of optical, electron, AFM and computational methods — with traceable calibration behind them — keep process control ahead of the geometry?